The present invention relates to an address translation apparatus in a virtual machine system, and more particularly to a control of a translation lookaside buffer suitable for the case where a number of virtual machines run in an address translation OFF mode.
In a virtual machine system, a single real machine is used time divisionally by setting virtual hardware information to each time slot so that the single real machine operates as if different machines run for respective time slots. Storage of a virtual machine is located on a virtual storage generated by a program (hereinafter referred to as a host) which supervises the real machine and realizes a virtual machine system. An access by a program (hereinafter referred to as a guest) running on a virtual machine, irrespective of whether it is a real or virtual address access, requires address translation by the host and storage in a translation look-aside buffer (hereinafter referred to as a TLB). A technique relevant to the system of this type is shown in, e.g., U.S. Pat. No. 4,456,954.
This conventional technique prepares two types of TLB entries for a host and presently running guest. There is disclosed in JP-B-58-8073 a method whereby the field of the TLB is extended by providing therein a virtual machine identification (hereinafter referred to as a VM identifier) for discrimination of a host and a plurality of guests. According to this method, the entries for both the host and, a plurality of guests are allowed to be present in the TLB at the same time, thus providing effective utilization of the TLB. A logical address stored in the TLB will be present therefore at high probability, thus improving the operation performance.
Further, according to JP-B-57-23347, an apparatus is disclosed wherein a space identifier and area identifier corresponding to the VM identifier are provided in a field of the TLB to discriminate among the address spaces of the host and a plurality of guests, thus realizing a multi virtual storage system.
The above conventional techniques are available on the assumption that the number of guests running at the same time is smaller than that capable of discrimination by a VM identifier. In the case where the number of guests running at the same time is larger than that a purge process of the TLB is required so that the advantageous performance of the above conventional techniques cannot be afforded. In order to solve such a problem, a sufficient number of bits may be assigned to a VM identifier. However, a VM identifier is a key element for the associative storage function of the TLB so that an increase in the bit number thereof results in an increased hardware cost.
Current address translation technology needs of a virtual machine system require an improved address translation operation that overcomes these problems and others to provide an address translation apparatus that has an advanced translation look-aside buffer for handling a number of guests without changing an interface of software and which reduces the overhead of address translation.